Title :
A Top-Down method for performance analysis and counters architecture
Author_Institution :
Archit. Group, Intel Corp., Hillsboro, OR, USA
Abstract :
Optimizing an application´s performance for a given microarchitecture has become painfully difficult. Increasing microarchitecture complexity, workload diversity, and the unmanageable volume of data produced by performance tools increase the optimization challenges. At the same time resource and time constraints get tougher with recently emerged segments. This further calls for accurate and prompt analysis methods. The insights from this method guide a proposal for a novel performance counters architecture that can determine the true bottlenecks of a general out-of-order processor. Unlike other approaches, our analysis method is low-cost and already featured in in-production systems - it requires just eight simple new performance events to be added to a traditional PMU. It is comprehensive - no restriction to predefined set of performance issues. It accounts for granular bottlenecks in super-scalar cores, missed by earlier approaches.
Keywords :
performance evaluation; software architecture; data volume; microarchitecture complexity; out-of-order processor; performance analysis; performance counters architecture; performance events; super-scalar cores; top-down method; workload diversity; Bandwidth; Electric breakdown; Measurement; Microarchitecture; Out of order; Pipelines; Radiation detectors;
Conference_Titel :
Performance Analysis of Systems and Software (ISPASS), 2014 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
978-1-4799-3604-5
DOI :
10.1109/ISPASS.2014.6844459