Title :
A comparative study of the behavior of NMOS and CMOS digital circuits under substrate noise
Author :
Secareanu, Radu M. ; Warner, Scott ; Seabridge, Scott ; Burke, Cathie ; Watrobski, Thomas E. ; Morton, Christopher ; Staub, William ; Tellier, Thomas ; Friedman, Eby G.
Author_Institution :
Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA
fDate :
6/23/1905 12:00:00 AM
Abstract :
A comparative study of the behavior of NMOS and CMOS digital circuits in terms of the ability to tolerate substrate noise is presented. Theoretical and simulation results are confirmed by experimental data gathered from the analysis of NMOS and CMOS test chips. It is shown that while the noise sensitivity of NMOS digital circuits is influenced by a variety of factors, the primary phenomenon responsible for the noise integrity of the CMOS digital circuits is latch-up
Keywords :
MOS integrated circuits; circuit simulation; integrated circuit noise; mixed analogue-digital integrated circuits; power integrated circuits; CMOS digital circuits; NMOS digital circuits; latch-up; mixed-signal smart-power environment; noise integrity; noise sensitivity; simulation results; substrate noise; Active noise reduction; CMOS digital integrated circuits; Circuit noise; Circuit testing; Digital circuits; Driver circuits; Latches; MOS devices; Substrates; Voltage;
Conference_Titel :
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN :
0-7803-7057-0
DOI :
10.1109/ICECS.2001.957710
