Capacitor less dram cell design for high performance embedded system

Author

Asthana, Prateek ; Mangesh, Sangeeta

Author_Institution

Dept. of Electron. & Commun., JSS Acad. of Tech. Educ., Noida, India

fYear

2014

fDate

24-27 Sept. 2014

Firstpage

554

Lastpage

559

Abstract

In this paper average power consumption and timing parameter i.e. read access time, write access time and retention time comparison of 3T1D DRAM is carried out. These analyses are carried out on 32nm scale. This DRAM cell is used in high performance embedded system. A technique is being used in the paper to improve average power consumption and read access time for 3T1D DRAM to make it more comparable to the SRAM 6T. A circuit to improve the average power consumption and the read access time of the 3T1D cell are analyzed. These circuits are analyzed on TANNER EDA. Circuits are designed on SEDIT and simulated on TSPICE.

Keywords

DRAM chips; SPICE; embedded systems; integrated circuit design; performance evaluation; power aware computing; 3T1D DRAM; SEDIT; SRAM 6T.A circuit; TANNER EDA; TSPICE; average power consumption; capacitor less DRAM cell design; high performance embedded system; read access time; retention time; timing parameter; write access time; Capacitors; MOSFET; Memory management; Power demand; Random access memory; Timing; 3T1D DRAM; DRAM; Low Power; Memory Design; TANNER EDA;

fLanguage

English

Publisher

ieee

Conference_Titel

Advances in Computing, Communications and Informatics (ICACCI, 2014 International Conference on

Conference_Location

New Delhi

Print_ISBN

978-1-4799-3078-4

Type

conf

DOI

10.1109/ICACCI.2014.6968474

Filename

6968474