The optimization of direct digital frequency synthesizer performance in the presence of finite word length effects

Techniques for the design of VLSI architectures for direct digital frequency synthesis have been introduced that allow for the optimization of the spurious response in the presence of finite-wordlength effects. These optimization techniques exploit certain number-theoretic properties of the phase accumulator to make the exhaustive simulation of direct digital frequency synthesizer (DDFS) performance in the presence of different system nonlinearities computationally feasible. These techniques have been applied to design a 14-bit-output DDFS with a simulated spurious performance of -90.3 dB and a level of pipelining that allows a 100-MHz clock rate in a 1.25-μm CMOS process