• DocumentCode
    1662284
  • Title

    Fast residue arithmetic multipliers based on signed-digit number system

  • Author

    Wei, Shugang ; Shimizu, Kensuke

  • Author_Institution
    Dept. of Comput. Sci., Gunma Univ., Japan
  • Volume
    1
  • fYear
    2001
  • fDate
    6/23/1905 12:00:00 AM
  • Firstpage
    263
  • Abstract
    Fast residue arithmetic multipliers based on a radix-2 signed-digit (SD) number are presented. For a given modulus m, 2p -1⩽m⩽ 2p+2p-1-1, in a residue number system (RNS), the modulo m addition is performed by using one or two p-digit SD adders, and the modulo m addition time is independent of the word length of operands. We propose two kinds of modulo m multipliers which are constructed using a modulo m SD adder and a binary tree of the adders and the modulo m multiplication are performed in a time proportional to p and log2p, respectively. 16-digit residue arithmetic multiplier circuits have been designed using VHDL, and the results show that high speed residue arithmetic circuits can be implemented
  • Keywords
    adders; hardware description languages; high-speed integrated circuits; integrated circuit design; logic CAD; multiplying circuits; residue number systems; trees (mathematics); SD adders; VHDL; binary tree; fast residue arithmetic multipliers; high speed residue arithmetic circuits; modulo m SD adder; modulo m addition; modulo m addition time; modulo m multiplication; modulo m multipliers; modulus; multiplication time; radix-2 signed-digit number; residue arithmetic multiplier circuits; residue number system; signed-digit number system; word length; Adders; Binary trees; Circuits; Computer science; Digital arithmetic; Equations;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
  • Print_ISBN
    0-7803-7057-0
  • Type

    conf

  • DOI
    10.1109/ICECS.2001.957730
  • Filename
    957730