• DocumentCode
    1662287
  • Title

    The T9000 transputer

  • Author

    May, Dominik ; Shepherd, Roderick ; Thompson, Peter

  • Author_Institution
    Inmos Ltd., Bristol, UK
  • fYear
    1992
  • Firstpage
    209
  • Lastpage
    212
  • Abstract
    Some of the issues arising in the design of the T9000 transputer, which integrates a complete computer in a single VLSI chip of over two million transistors, are discussed. High performance has been achieved by extensive use of caching and a novel processor implementation. The processor uses a fat pipeline and dispatches several dependent instructions into the pipeline each cycle. The resulting processor is able to saturate a 25-MFLOP floating-point unit. The processor is supported by a communications system that supports communications at high speed and low latency
  • Keywords
    VLSI; digital arithmetic; transputers; 25-MFLOP floating-point unit; T9000 transputer; caching; communications system; fat pipeline; high speed; low latency; single VLSI chip; Bandwidth; Bidirectional control; Communication switching; Communication system control; Memory architecture; Memory management; Microprocessors; Silicon; Switches; Virtual colonoscopy;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
  • Conference_Location
    Cambridge, MA
  • Print_ISBN
    0-8186-3110-4
  • Type

    conf

  • DOI
    10.1109/ICCD.1992.276250
  • Filename
    276250