Three dimensional circuit oriented electromagnetic modeling for VLSI interconnects

A general approach for modeling 3-D layout geometries is presented. In particular, the partial-element equivalent circuit (PEEC) technique has been used successfully to model interconnect structures for chips and packages. The technique, which is circuit based, permits the electrical modeling of arbitrary 3-D geometries and allows 3-D transmission line properties to be analyzed. Recently, the technique has been extended to include retardation and dielectric layers. The authors have experimented with the use of the asymptotic waveform evaluation (AWE) approach to speed up the solution of the resulting circuit equations