Numerical study of non-classical unipolar CMOS with different embedded oxide and gate length

Author

Sun, Chih-Hung ; Lin, Jyi-Tsong ; Chen, Hsuan-Hsu ; Eng, Yi-Chuen ; Kuo, Chih-Hao ; Chang, Tze-Feng ; Chen, Chun-Yu ; Lin, Po-Hsieh ; Chiu, Hsien-Nan

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

fYear

2010

Firstpage

21

Lastpage

24

Abstract

In this paper, we propose a novel unipolar CMOS device with embedded oxide. Good inverter and logic gate output waveforms and behaviors are obtained. Utilizing the punch through effect, the Non-Classical Unipolar CMOS is demonstrated to enhance the t_PLH so that the average delay time can be improved 23% when compared with the conventional CMOS. Due to all NMOS structures are only exploited and the common electrodes areas are shared, the layout area can be reduced more than 71%, which leads to significantly increase on the packaging density of CMOS circuits.

Keywords

CMOS integrated circuits; electrodes; integrated circuit packaging; CMOS circuit packaging density; NMOS structures; gate length; logic gate output waveform; nonclassical unipolar CMOS; unipolar CMOS device; CMOS integrated circuits; Integrated circuit modeling; Production; Semiconductor device modeling; delay time; packaging density; punch through effect; unipolar CMOS;

fLanguage

English

Publisher

ieee

Conference_Titel

Next-Generation Electronics (ISNE), 2010 International Symposium on

Conference_Location

Kaohsiung

Print_ISBN

978-1-4244-6693-1

Type

conf

DOI

10.1109/ISNE.2010.5669137

Filename

5669137