Title :
CESL deposition promoting n/p MOSFETs under 45-nm-node process fabrication
Author :
Wang, Mu-Chun ; Yang, Hsin-Chia ; Liao, Wen-Shiang ; Yang, Hsiu-Yen ; Hoe, Yao-Yuan ; Lin, Kuang-Hung ; Chen, Shuang-Yuan
Author_Institution :
Dept. of Electron. Eng., Ming Hsin Univ. of Sci. & Technol., Hsinchu, Taiwan
Abstract :
In this study, the process technology of contact-etching stop-layer (CESL) with LPCVD or PECVD is performed by interlayer-dielectric-SiNx stressing layer to form the tensile or compressive strained n/p MOSFETs. Because the strain effect on MOSFET devices is finite, the promoting performance of source/drain current is increased more while the channel lengths of the devices are decreased more. This phenomenon is obviously observed with devices, width/length=W/L= 10/10 and 10/.08 (μm/μm). Moreover, the trend evidence for tensile strain benefited to nMOSFETs and pMOSFETs, but for compressive strain favoring pMOSFTEs and not hugely degrading nMOSFETs, is also achieved.
Keywords :
Ge-Si alloys; MOSFET; compressive strength; dielectric materials; etching; laser deposition; plasma CVD; silicon compounds; tensile strength; CESL deposition; MOSFET devices; SiGe; compressive strain; contact-etching stop-layer; for tensile strain; interlayer-dielectric-SiN<;sub>x<;/sub> stressing layer; n-p MOSFET; source-drain current; MOSFET circuits; MOSFETs; CESL; MOSFET; SiGe channel; strained silicon technology;
Conference_Titel :
Next-Generation Electronics (ISNE), 2010 International Symposium on
Conference_Location :
Kaohsiung
Print_ISBN :
978-1-4244-6693-1
DOI :
10.1109/ISNE.2010.5669140