DocumentCode
1662553
Title
Comparative study of strategies for formal verification of high-level processors
Author
Velev, Miroslav N.
fYear
2004
Firstpage
119
Lastpage
124
Abstract
Different methods are compared for the evaluation of formulas expressing microprocessor correctness in the logic of equality with uninterpreted functions and memories (EUFM) by translation to prepositional logic, given recently developed efficient Boolean-to-CNF translations, in order to identify the best overall translation strategy from EUFM to CNF. The translation from EUFM to propositional logic is done by exploiting the property of positive equality, allowing us to treat most of the abstract word-level values as distinct constants while performing complete formal verification. For EUFM formulas from correct microprocessors, the best translation was by using the eij encoding of g-equations (dual-polarity equations), the nested-ITE scheme for the elimination of uninterpreted predicates, preserving the ITE-tree structure of equation arguments, and Boolean-to-CNF translation by encoding the unobservability of logic blocks by merging them with adjacent gates on the only path to the primary output. For EUFM formulas from buggy microprocessors, the best translation was by using the eij encoding of g-equations, the Ackermann scheme for the elimination of uninterpreted predicates, preserving the ITE-tree structure of equation arguments, and Boolean-to-CNF translation by applying optimizations to reduce the number of clauses - merging of ITE-trees with one level of their AND/OR leaves, and exploiting the polarity of gates and logic blocks to reduce the number of their clauses.
Keywords
Boolean functions; formal verification; logic gates; microprocessor chips; optimisation; AND-OR gates; Boolean functions; ITE tree structure; conjunction normal formulas; dual polarity equations; encoding; equality with uninterpreted functions and memories; formal verification; high level processors; microprocessors; optimization; propositional logic; Boolean functions; Encoding; Equations; Formal verification; Logic gates; Merging; Microprocessors; Predictive models; Productivity; Read-write memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on
ISSN
1063-6404
Print_ISBN
0-7695-2231-9
Type
conf
DOI
10.1109/ICCD.2004.1347910
Filename
1347910
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