• DocumentCode
    1662610
  • Title

    Linear programming for optimum hazard elimination in asynchronous circuits

  • Author

    Lavagno, L. ; Sangiovanni-Vincentelli, A.

  • Author_Institution
    Dept. of EECS, California Univ., Berkeley, CA, USA
  • fYear
    1992
  • Firstpage
    275
  • Lastpage
    278
  • Abstract
    It is shown that hazards can be optimally eliminated from circuits synthesized starting with a signal transition graph (STG) specification. The proposed approach is based on a linear programming (or integer linear programming) formulation, and as such it can be solved efficiently and optimally for a variety of cost functions. Suggested cost functions optimize either the total padded delay, an estimate of the increase in area, or the maximum cycle time of the complete system. It is also shown that delay padding on all fanouts of STG signals is a necessary and sufficient condition for hazard elimination if the structure and delay of each combinational logic block cannot be changed. Experimental results indicate that the improvements obtained are well worth the added complexity of linear program solution
  • Keywords
    asynchronous sequential logic; computational complexity; formal verification; linear programming; logic circuits; asynchronous circuits; combinational logic block; complexity; cost functions; linear programming; maximum cycle time; necessary and sufficient condition; optimum hazard elimination; signal transition graph; specification; total padded delay; Circuit synthesis; Cost function; Delay effects; Delay estimation; Hazards; Integer linear programming; Linear programming; Logic; Signal synthesis; Sufficient conditions;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
  • Conference_Location
    Cambridge, MA
  • Print_ISBN
    0-8186-3110-4
  • Type

    conf

  • DOI
    10.1109/ICCD.1992.276268
  • Filename
    276268