DocumentCode
1662741
Title
Implementation of spaceborne SAR imaging processor based on FPGA
Author
Yizhuang, Xie ; Teng, Long
Author_Institution
Radar Res. Lab., Beijing Inst. of Technol., Beijing
fYear
2008
Firstpage
2318
Lastpage
2321
Abstract
With the rapid development of FPGA and its technology characteristic, this paper puts forward that FPGA is an effective and realizable technical approach for future spaceborne SAR imaging processor. With the ready-researched FPGA processor, the implementation architecture of spaceborne SAR imaging processor is studied. Further more, R-D quick look algorithm of spaceborne SAR is analyzed and mapped to the FPGA processor, each processing node of the FPGA processor uses different implementation architectures to image with the spaceborne SAR simulation raw data under the way of pipeline processing.
Keywords
field programmable gate arrays; radar imaging; spaceborne radar; synthetic aperture radar; R-D quick look algorithm; pipeline processing; ready-researched FPGA processor; spaceborne SAR imaging processor; synthetic aperture radar; Azimuth; Bandwidth; Field programmable gate arrays; Frequency domain analysis; High-resolution imaging; Image coding; Image resolution; Radar polarimetry; Signal processing; Spaceborne radar;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing, 2008. ICSP 2008. 9th International Conference on
Conference_Location
Beijing
Print_ISBN
978-1-4244-2178-7
Electronic_ISBN
978-1-4244-2179-4
Type
conf
DOI
10.1109/ICOSP.2008.4697613
Filename
4697613
Link To Document