• DocumentCode
    1662745
  • Title

    Estimating lower-bound performance of schedules using a relaxation technique

  • Author

    Rim, Minjoong ; Jain, Rajiv

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
  • fYear
    1992
  • Firstpage
    290
  • Lastpage
    294
  • Abstract
    A technique for computing a lower bound for nonpipelined resource-constrained scheduling performance is presented. Given a data-flow graph, a set of resources, resource delays, and clock cycle, a lower bound on the performance of a schedule is derived. The technique is fast (typical runtime of 50 ms), and the experimental lower-bounds are within two time steps of the actual schedules produced by a scheduling heuristic. The technique is also constructive and can be incorporated in a branch-and-bound method for solving the scheduling problem. The lower bound can be used to reduce a design search space. The method is applicable to lower-bound estimation in high-level synthesis
  • Keywords
    circuit CAD; delays; resource allocation; scheduling; branch-and-bound method; clock cycle; data-flow graph; high-level synthesis; lower bound performance estimation; nonpipelined resource-constrained scheduling performance; relaxation technique; resource delays; schedules; scheduling heuristic; Clocks; Delay; Flow graphs; Greedy algorithms; High level synthesis; Integer linear programming; Processor scheduling; Runtime;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
  • Conference_Location
    Cambridge, MA
  • Print_ISBN
    0-8186-3110-4
  • Type

    conf

  • DOI
    10.1109/ICCD.1992.276272
  • Filename
    276272