DocumentCode
1662775
Title
Low power test data compression based on LFSR reseeding
Author
Lee, Jinkyu ; Touba, Nur A.
Author_Institution
Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
fYear
2004
Firstpage
180
Lastpage
185
Abstract
Many test data compression schemes are based on LFSR reseeding. A drawback of these schemes is that the unspecified bits are filled with random values resulting in a large number of transitions during scan-in thereby causing high power dissipation. This paper presents a new encoding scheme that can be used in conjunction with any LFSR reseeding scheme to significantly reduce test power and even further reduce test storage. The proposed encoding scheme acts as a second stage of compression after LFSR reseeding. It accomplishes two goals. First, it reduces the number of transitions in the scan chains (by filling the unspecified bits in a different manner), and second, it reduces the number of specified bits that need to be generated via LFSR reseeding. Experimental results indicate that the proposed method significantly reduces test power and in most cases provides greater test data compression than LFSR reseeding alone.
Keywords
encoding; logic testing; low-power electronics; shift registers; LFSR reseeding; encoding; low power test data compression; power dissipation; shift registers; test power reduction; Data engineering; Encoding; Energy consumption; Filling; Power dissipation; Power engineering and energy; Power engineering computing; System-on-a-chip; Test data compression; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on
ISSN
1063-6404
Print_ISBN
0-7695-2231-9
Type
conf
DOI
10.1109/ICCD.2004.1347919
Filename
1347919
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