NVAX and NVAX+: single-chip CMOS VAX microprocessors

Author

Bernstein, Debra ; Brown, John F., III ; Stamm, Rebecca L. ; Uhler, G. Michael

Author_Institution

Digital Equipment Corp., Hudson, MA, USA

fYear

1992

Firstpage

302

Lastpage

305

Abstract

A description is given of NVAX and NVAX+, single-chip microprocessors that implement Digital Equipment Corporation´s VAX architecture. Pipelining techniques that have traditionally been associated with RISC CPUs are used to greatly improve the performance of these chips over previous VAX microprocessors. Successful application of these techniques requires careful consideration of memory request and operand request ordering, I/O space access, and multiprocessor issues. NVAX provides an upgrade path to customers having existing systems which use a previous VAX microprocessor. NVAX+ provides a migration path to customers who choose to convert NVAX+ systems to use the DECchip 21064 ALPHA microprocessor

Keywords

CMOS integrated circuits; VLSI; microprocessor chips; reduced instruction set computing; DECchip 21064 ALPHA microprocessor; Digital Equipment Corporation´s VAX architecture; I/O space access; NVAX; NVAX+; RISC CPUs; memory request; migration path; operand request ordering; pipelining techniques; single-chip CMOS VAX microprocessors; CMOS process; Decoding; Heart; Microprocessors; Operating systems; Pipeline processing; Prefetching; Read-write memory; Reduced instruction set computing; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-3110-4

Type

conf

DOI

10.1109/ICCD.1992.276275

Filename

276275