Dynamic reordering of high latency transactions using a modified micropipeline

An asynchronous architecture for dynamically reordering sequences of instructions issued to a processing element is presented. The optimizations supported are the exchange of two instructions and the cancellation of an instruction using its predecessor. The design is a modification of I. Sutherland´s (1989) micropipeline, and is called the asynchronous reordering micropipeline (ARM). The optimizations to be effected by the ARM are captured using rewrite rules that transform instruction subsequences into more optimal (and semantically equivalent) subsequences. One application of the ARM is in optimizing transactions issued to a system called the rollback chip (RBC), which is used to accelerate the state-saving and rollback activities performed by a processing node when it runs distributed discrete-event simulation using time warp