DocumentCode
1662979
Title
A mixed mode perceptron cell for VLSI neural networks
Author
Camboni, Fausto ; Valle, Maurizio
Author_Institution
Microelectron. Lab., Genoa Univ., Italy
Volume
1
fYear
2001
fDate
6/23/1905 12:00:00 AM
Firstpage
377
Abstract
A reconfigurable mixed-mode perceptron building block for VLSI neural networks is presented. The proposed architecture is suitable for high-speed low-power neural networks like multi layer perceptrons. The proposed system uses a mixed-signal multiplier technique for directly multiplying the digital weights and the analog input signals. A 5-input 6-bit design has been simulated in a 0.6 μm CMOS process. The perceptron operates up to 125 MHz and dissipates 2 mW. The power efficiency is 300 MCPS/mW
Keywords
CMOS integrated circuits; VLSI; low-power electronics; mixed analogue-digital integrated circuits; multilayer perceptrons; multiplying circuits; neural chips; 0.6 micron; 125 MHz; 2 mW; 6 bit; CMOS; VLSI; low-power design; mixed-signal multiplier technique; multi layer perceptrons; neural networks; power efficiency; reconfigurable mixed-mode perceptron cell; Biophysics; CMOS process; Circuit simulation; Electronic mail; Energy consumption; Equations; Laboratories; Microelectronics; Neural networks; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN
0-7803-7057-0
Type
conf
DOI
10.1109/ICECS.2001.957758
Filename
957758
Link To Document