• DocumentCode
    1663082
  • Title

    Potential slack budgeting with clock skew optimization

  • Author

    Wang, Kai ; Sadowska, Malgorzata Marek

  • Author_Institution
    Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
  • fYear
    2004
  • Firstpage
    265
  • Lastpage
    271
  • Abstract
    Potential slack is an effective metric of circuit´s possible performance improvement. It is equal to the maximal amount of slack that can be potentially used for optimization. In this paper, we first present a new, linear programming-based approach for potential slack calculation. Our method produces an optimal solution with significant runtime speedup compared to previous methods. Then, we formulate and solve the problem of global potential slack budgeting by clock-skew optimization. We demonstrate experimentally that the potential slack can be significantly improved by appropriate clock skew assignment.
  • Keywords
    circuit optimisation; linear programming; logic circuits; clock skew optimization; linear programming; logic circuits; potential slack budgeting; Circuit testing; Clocks; Computational efficiency; Cost function; Delay; Design optimization; Logic; Power dissipation; Space exploration; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on
  • ISSN
    1063-6404
  • Print_ISBN
    0-7695-2231-9
  • Type

    conf

  • DOI
    10.1109/ICCD.2004.1347932
  • Filename
    1347932