Implementation of the one dimensional discrete cosine transform using the residue number system

Author

Femandez, P.G. ; Ramirez, J. ; Garcia, A. ; Parrilla, L. ; Lloris, A.

Author_Institution

Dept. of Electr. Eng., Jaen Univ., Spain

Volume

1

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

433

Abstract

This paper shows the implementation of the one dimensional discrete cosine transform (1D-DCT) based on the residue number system (RNS). The 1D-DCT has been derived by,the application of a previously developed scaled fast cosine transform (FCT) algorithm that requires a reduced number of multiplications. The processor has been modeled at structural level using VHDL and implemented in Altera FLEX10K devices. This paper shows that the RNS-enabled ID-DCT provides a throughput improvement over the equivalent binary system of up to 62% when 8-bit moduli are used. This is achieved due to the synergy between RNS and modern field programmable logic (FPL) device families

Keywords

data compression; digital signal processing chips; discrete cosine transforms; field programmable gate arrays; hardware description languages; image processing equipment; integrated circuit design; integrated circuit modelling; residue number systems; video coding; 1D discrete cosine transform implementation; 1D-DCT implementation; 8 bit; Altera FLEX10K device implementation; RNS-enabled 1D-DCT; VHDL; field programmable logic device; image processing; moduli; multiplications; residue number system; scaled fast cosine transform algorithm; structural level processor model; video signal coding; Arithmetic; Digital signal processing; Discrete cosine transforms; Discrete transforms; Dynamic range; Image coding; Logic devices; Programmable logic arrays; Signal processing algorithms; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957772

Filename

957772