DocumentCode
1663349
Title
On limitations and extensions of STG model for designing asynchronous control circuits
Author
Yakovlev, A.V.
Author_Institution
Dept. of Comput. Sci., Newcastle upon Tyne Univ., UK
fYear
1992
Firstpage
396
Lastpage
400
Abstract
A number of limitations of the current status of signal transition graphs (STGs), a model which has recently become popular for designing asynchronous interface circuits, are discussed. The major syntactic and semantic restrictions that can be lifted are safety, free-choice net structure and binary signal labeling. A number of instructive examples of interface control circuit specifications, which are semantically correct yet free from such restrictions, are presented. Adequate techniques for analysis and implementation of the extended STG model are discussed
Keywords
graph theory; network synthesis; system buses; STG model; asynchronous control circuits; asynchronous interface circuits; binary signal labeling; free-choice net structure; interface control circuit specifications; semantic restrictions; signal transition graphs; Circuit synthesis; Concurrent computing; Delay; Labeling; Logic; Petri nets; Safety; Signal design; Signal synthesis;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
Conference_Location
Cambridge, MA
Print_ISBN
0-8186-3110-4
Type
conf
DOI
10.1109/ICCD.1992.276300
Filename
276300
Link To Document