A delta-sigma frequency synthesizer with enhanced phase noise performance

Fractional-N frequency synthesis has been introduced to alleviate integer-N Phase Locked Loop (PLL) frequency resolution problems as the requirement for fast switching time and low phase noise become increasingly stringent. Since its introduction, many Fractional-N PLL architectures have been implemented. However, these architectures, although they solve the frequency resolution issue, also generate other unwanted problems. It is the aim of this paper to outline those problems as well as provide a new fractional-N architecture that significantly alleviates the problems. The new architecture has been implemented in sub-micron RFCMOS technology. Measured phase noise results satisfy several cellular system requirements.