An IEEE 1149.1 compliant testability architecture with internal scan

A testability architecture for VLSI devices which is IEEE 1149.1 compliant and includes extensions for partitionable internal scan chains is described. The architecture includes a fully synchronous scan cell library and an explicit synchronization barrier between test clock synchronous logic and system clock synchronous logic. The explicit synchronization barrier guarantees coherent sampling of device state. These techniques result in VLSI designs that are amenable to static timing analysis and are extensible to at-speed built-in-self-test (BIST). Results for five VLSI devices used in the CM5, a massively parallel supercomputer, show low logic overhead (8-20%) and high in-system stuck-at fault coverage (>99.5%)