Design of high-speed analog-to-digital interface in digital technologies

Author

Uyttenhove, Koen ; Steyaert, Michiel

Author_Institution

ESAT, Katholieke Univ. Leuven, Heverlee, Belgium

Volume

1

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

493

Abstract

Analog design in deep sub-micron digital technologies is a reality now and poses severe challenges to the circuit designer. Trends in digital technologies as well as their effects on analog circuits axe discussed. The typical speed-power-accuracy trade-off in analog design is revised with respect to the technological modifications. A new speed model includes slew rate behaviour together with settling behaviour. Calculations show a possible increase in power for future generations of high speed analog-to-digital converters

Keywords

VLSI; analogue-digital conversion; high-speed integrated circuits; integrated circuit design; monolithic integrated circuits; analog design; analog-todigital converters; deep submicron digital technologies; flash ADC; high-speed analog/digital interfaces; settling behaviour; slew rate behaviour; speed model; speed-power-accuracy tradeoff; Analog circuits; Analog-digital conversion; Communications technology; Digital signal processing; Power generation; Power system modeling; Radar signal processing; Signal generators; Signal resolution; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957786

Filename

957786