A 72dB-DR ΔΣ CT modulator using digitally estimated auxiliary DAC linearization achieving 88fJ/conv in a 25MHz BW

The ongoing trend for wide-band, power-efficient continuous-time ΔΣ modulators has led to various implementations, which commonly share the usage of multi-bit quantization, low oversampling ratio and 3^rd or 4^th-order loop-filters [1,2]. In order to improve power efficiency, circuit and architectural innovations [1], as well as digital implementation [3] or digital correction of analog circuit parts have been used. To date, the best power vs. performance ratio for ΔΣ modulators with above 10MHz bandwidth is held by [1] with an FoM of 120fJ/conv.