Title :
An improved high-level built-in self-test synthesis algorithm
fDate :
6/23/1905 12:00:00 AM
Abstract :
In this paper, we describe an improved high-level built-in self-test synthesis algorithm for operation scheduling and data path allocation. It generates highly self-testable data path design while maximizing the sharing of test registers, which means only a small number of registers is modified for BIST. The algorithm also produces design with high test concurrency, thereby decreasing test time. In our previous work (Yang and Muzio, 2001), we have proposed an integrated operation scheduling and data path allocation approach for built-in self-testable designs. In this study, we mainly make use of some concepts and techniques to improve the previous work during the operation scheduling part, especially to determine the execution order of different operations when rescheduling transformations are performed. With a variety of benchmarks, we demonstrate the advantage of our approach compared with other conventional approaches
Keywords :
VLSI; built-in self test; circuit CAD; high level synthesis; integrated circuit design; integrated circuit testing; scheduling; BIST; VLSI circuit testability; VLSI technology; built-in self-test; built-in self-testable design; data path allocation; execution order; high-level built-in self-test synthesis algorithm; high-level synthesis algorithm; integrated operation scheduling/data path allocation; maximized test register sharing; operation scheduling; register modification; rescheduling transformations; self-testable data path design; test concurrency; test time; Algorithm design and analysis; Automatic testing; Built-in self-test; Circuit testing; Computer science; Concurrent computing; Hardware; Scheduling algorithm; Throughput; Very large scale integration;
Conference_Titel :
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN :
0-7803-7057-0
DOI :
10.1109/ICECS.2001.957802
