Title :
Placement with alignment and performance constraints using the B*-tree representation
Author :
Wu, Meng-Chen ; Chang, Yao-Wen
Author_Institution :
Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
To facilitate sequential data transfer (e.g., bus or pipeline signals) and reduce bounded net delay (as well as total wirelength), it is desired to align circuit blocks one by one and constrain the blocks within a certain bounding box. In this paper, we handle the placement with alignment and performance (delay) constraints using the B*-tree representation. We first explore the feasibility conditions with the alignment and performance constraints, and then propose algorithms that can guarantee a feasible placement with alignment constraints and generate a good placement with performance constraints during each operation. In particular, our method is the first algorithm to achieve the amortized linear-time complexity for evaluating a placement with the alignment and performance constraints. Experimental results based on the MCNC benchmark with the constraints show that our method significantly outperforms the previous work.
Keywords :
circuit complexity; integrated circuit layout; trees (mathematics); B-tree representation; benchmark circuits; bounded net delay; circuit blocks; delay constraints; integrated circuit layout; linear time complexity; sequential data transfer; Binary trees; Circuits; Data engineering; Delay; Merging; Pipelines; Routing; Shape; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on
Print_ISBN :
0-7695-2231-9
DOI :
10.1109/ICCD.2004.1347979