A NoC based distributed memory architecture with programmable and partitionable capabilities

The paper focuses on the design of a Network-on-chip based programmable and partitionable distributed memory architecture which can be integrated with a Coarse Grain Reconfigurable Architecture (CGRA). The proposed interconnect enables better interaction between computation fabric and memory fabric. The system can modify its memory to computation element ratio at runtime. The extensive capabilities of the memory system are analyzed by interfacing it with a Dynamically Reconfigurable Resource Array (DRRA), a CGRA. The interconnect can provide multiple interfaces which supports upto 8 GB/s per interface.