Automated RTR temporal partitioning for reconfigurable embedded real-time system design

We present an automated temporal partitioning applied on the data-path part of an algorithm for reconfigurable embedded system design. This temporal partitioning, included in a design space exploration methodology, uses trade-offs in time constraint, design size and FPGA device parameters (circuit speed, reconfiguration time). The originality of this partitioning is that it minimizes the number of cells needed to implement the data-path of an application under a time constraint by taking into account the needs of bandwidth and memory size. This approach allows avoiding an oversizing of the implementation resources needed. This optimizing approach can be useful for the design of a dynamically reconfigurable embedded device or system. We illustrate our approach in the real time image processing field.