Fault simulation and response compaction in full scan circuits using HOPE

This paper presents results on fault simulation and response compaction on ISCAS 89 full scan sequential benchmark circuits using HOPE-a fault simulator developed for synchronous sequential circuits that employs parallel fault simulation with heuristics to reduce simulation time in the context of design space-efficient support hardware for built-in self-testing of VLSI circuits. The techniques utilized in the paper take advantage of sequence characterization developed previously by the authors for response data compaction in the case of ISCAS 85 combinational benchmark circuits, using ATALANTA, FSIM, and COMPACTEST, under conditions of both stochastic independence and dependence of single and double line errors, and then apply these concepts to the case of full scan sequential benchmark circuits using the fault simulator HOPE.