• DocumentCode
    1666288
  • Title

    Is RF doomed to digitization? What shall RF circuit designers do?

  • Author

    Staszewski, R. Bogdan ; Rudell, Jacques

  • Author_Institution
    Delft Univ. of Technol., Delft, Netherlands
  • fYear
    2012
  • Firstpage
    510
  • Lastpage
    510
  • Abstract
    To support the ever-increasing levels of system-on-chip (SoC) integration required by the consumer insatiate appetite for sophisticated yet cheap mobile phones and internet devices, the RF circuit design has recently been moving to the finer CMOS process geometry nodes. There, it can harness the enormous potential of nearly free digital logic and memory. Enter the digital assistance of RF, which offers calibration, compensation, linearization and predistortion of linear devices, which can boost the RF system performance to the point that it is now better and more reliable than with the conventional approaches. The related field of RF built-in self-test (RF-BIST) allows for an RF-SoC to exploit the power of digital signal processing to autonomously test its own RF almost for free. Enter “digital RF”, which transforms the continuous-time analog RF functionality into digitally-intensive or even all-digital implementations. With the transition frequency fT of over 200MHz in 40nm CMOS, the RF circuits operating at 2GHz now feel just almost like the low-frequency mixed-signal circuits of the past.
  • Keywords
    CMOS logic circuits; CMOS memory circuits; built-in self test; calibration; digital signal processing chips; integrated circuit design; mixed analogue-digital integrated circuits; mobile handsets; radiofrequency integrated circuits; system-on-chip; CMOS process geometry nodes; EP1; Internet devices; RF built-in self-test; RF circuit designers; RF digital assistance; RF system performance; RF-SoC; continuous-time analog RF functionality; digital logic; digital memory; digital signal processing; digitally-intensive implementations; frequency 2 GHz; linear devices predistortion; low-frequency mixed-signal circuits; mobile phones; size 40 nm; system-on-chip integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    978-1-4673-0376-7
  • Type

    conf

  • DOI
    10.1109/ISSCC.2012.6177041
  • Filename
    6177041