Current consumption dynamics at instruction and program level for a VLIW DSP processor

The paper describes a new methodology for analyzing low-level current dynamics at the instruction level and the program level for a VLIW DSP processor core. An efficient methodology for software power analysis is presented, which, unlike other research supports dynamic current analysis and complex VLIW processor cores. Analysis of high bank register allocation, equivalent functional construct usage, and program-based current, power, and energy is presented. The basic principles and methods developed throughout this research are general and applicable to complex pipelined processors. The research is important for analyzing and designing secure power-efficient DSP embedded applications.