Title :
Over-10×-extended-lifetime 76%-reduced-error solid-state drives (SSDs) with error-prediction LDPC architecture and error-recovery scheme
Author :
Tanakamaru, Shuhei ; Yanagihara, Yuki ; Takeuchi, Ken
Author_Institution :
Univ. of Tokyo, Tokyo, Japan
Abstract :
This paper presents solid-state drives (SSDs) with two high reliability techniques. First, an error-prediction (EP) low-density-parity-check (LDPC) error-correcting code (ECC) that realizes an over 10× extended lifetime. Second, an error-recovery (ER) scheme that decreases the program-disturb error rate and the data-retention error rate by 74% and 56%, respectively.
Keywords :
disc drives; error correction codes; integrated memory circuits; parity check codes; data-retention error rate; error-prediction LDPC architecture; error-recovery scheme; high reliability techniques; low-density-parity-check error-correcting code; program-disturb error rate; solid-state drives; Bit error rate; Couplings; Error correction codes; Flash memory; Nonvolatile memory; Parity check codes; Reliability;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-0376-7
DOI :
10.1109/ISSCC.2012.6177074
