Noise-tolerance analysis for high speed CMOS circuits

Author

Graziano, Mariagrazia ; Masera, Guido ; Piccinini, Gianluca ; Roch, Massirno Ruo ; Zamboni, Maurizio

Author_Institution

Dipt. di Elettronica, Politecnico di Torino, Italy

fYear

1998

fDate

6/20/1905 12:00:00 AM

Firstpage

37

Lastpage

40

Abstract

The noise tolerance of new submicron logic families is becoming more and more important for the reliability of high speed architectures. A method for the evaluation of noise robustness must be defined to compare different topologies and help designers in the library cells optimization, The paper describes a methodology for the analysis of self induced noise tolerance based on the statistical simulation of noise sources. This method can be usefully applied in the study of parasitics due to interconnections crosstalk in digital design and to the substrate-coupling in ICs

Keywords

CMOS logic circuits; circuit CAD; circuit simulation; crosstalk; high-speed integrated circuits; integrated circuit noise; integrated circuit testing; automatic CAD program; digital design; distributed modelling; high speed CMOS circuits; interconnections crosstalk; library cells optimization; noise robustness; noise sources; noise-tolerance analysis; parasitics; reliability; self induced noise tolerance; statistical simulation; submicron logic families; substrate-coupling; CMOS logic circuits; Circuit noise; Circuit topology; Clocks; Crosstalk; Integrated circuit interconnections; Integrated circuit noise; Logic devices; Logic testing; Noise level;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 1998. ICM '98. Proceedings of the Tenth International Conference on

Conference_Location

Monastir

Print_ISBN

0-7803-4969-5

Type

conf

DOI

10.1109/ICM.1998.825562

Filename

825562