DocumentCode
1667559
Title
Dynamic CMOC noise immunity
Author
Kabbani, A. ; Al-Khalili, A.J.
Author_Institution
Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
fYear
1998
fDate
6/20/1905 12:00:00 AM
Firstpage
41
Lastpage
44
Abstract
While dynamic CMOS logic is considered an attractive circuit technique, it is suffering from noise problems. Noise may affect dynamic CMOS circuits in many ways. In this paper new models have been developed considering a noise pulse on one of the circuit inputs or on the clock input. These models specify the circuit noise immunity in terms of both the amplitude and the duration of a noise pulse. HSPICE simulations confirm the validity of these models
Keywords
CMOS logic circuits; SPICE; integrated circuit modelling; integrated circuit noise; HSPICE simulation; analytical model; dynamic CMOS logic circuit; noise immunity; CMOS logic circuits; CMOS technology; Circuit noise; Clocks; Noise level; Pulse circuits; Semiconductor device modeling; Signal to noise ratio; Space vector pulse width modulation; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics, 1998. ICM '98. Proceedings of the Tenth International Conference on
Conference_Location
Monastir
Print_ISBN
0-7803-4969-5
Type
conf
DOI
10.1109/ICM.1998.825563
Filename
825563
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