• DocumentCode
    1667574
  • Title

    Reduced distribution of threshold voltage shift in double layer NiSi2 nanocrystals for nano-floating gate memory applications

  • Author

    Choi, Sung-Jin ; Lee, Jun-Hyuk ; Kim, Dong-Hyoun ; Oh, Seul-ki ; Song, Wangyu ; Choi, Seon-Jun ; Lee, Seung-Beck

  • Author_Institution
    Dept. of Nanoscale Semicond. Eng., Hanyang Univ., Seoul, South Korea
  • fYear
    2010
  • Firstpage
    1246
  • Lastpage
    1247
  • Abstract
    We report on the fabrication and C-V characteristics of double layer NiSi2 nanocrystals (NCs) with Si3N4 interlayer tunnel barrier for nano-floating gate memory applications. The variation in threshold voltage shift (¿VTH) was measured for samples at different stress voltages. The ¿VTH increased with applied program voltage from 1.0 V at 3 V to 2.3 V at 7 V. Compared with SiO2 distribution of ¿VTH is reduced to 0.2~0.4 V in each program voltages demonstrating possible multi-level-cell (MLC) operation.
  • Keywords
    flash memories; nanofabrication; nanostructured materials; nickel alloys; silicon alloys; silicon compounds; storage media; C-V characteristics; NiSi2-Si3N4-SiO2; double layer nanocrystals; interlayer tunnel barrier; multilevel-cell operation; nanofloating gate memory applications; program voltages; stress voltages; threshold voltage shift; voltage 1.0 V to 2.3 V; voltage 3 V; voltage 7 V; Capacitance-voltage characteristics; Chromium; Electrodes; Fabrication; Gold; Nanocrystals; Nanostructures; Sputtering; Temperature measurement; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Nanoelectronics Conference (INEC), 2010 3rd International
  • Conference_Location
    Hong Kong
  • Print_ISBN
    978-1-4244-3543-2
  • Electronic_ISBN
    978-1-4244-3544-9
  • Type

    conf

  • DOI
    10.1109/INEC.2010.5424920
  • Filename
    5424920
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1667574