Implementation of a PCI bus virtual driver using PLI, named pipes, and signals

In designing a complex ASIC it is often the case that adequate testing cannot be performed without modeling the high level environment where the ASIC will eventually reside. One approach for developing these models is to write a description of the environment in the native simulation language (Verilog or VHDL) that is being used to develop the ASIC. While designing a complex ATM network interface chip with a PCI bus interface it became necessary to develop a driver model to check correctness of operation. We decided to develop a co-design environment which would allow us to develop a real driver (in C++) which would interact with the current hardware model in RTL. This would benefit the project in two ways. First the driver writer would not need to learn a new language and could re-use code, and secondly, there would be a fully developed driver when the chip was ready to be tested. This approach, which uses UNIX named pipes and signals, allowed us to have driver software written before the chip had been manufactured and facilitated our regression methodology. This paper describes the architecture of the simulation interface