Practical transient system-level ESD modeling - Environment contribution

A methodology for building a transient model of an analog system is detailed. It does not require proprietary knowledge for integrated circuits (IC). At IC level, it combines a protection structure characterization and behavioral modeling with a core description. A specific test board is developed with a smart voltage regulator to validate the methodology. A system model is assembled to perform powered-on transient ESD simulations. A soft-failure criterion is chosen and the prediction of trends in soft-failure generation is carried out. The strong influence of the electrical environment is demonstrated through this case study.