Evaluation of High-Speed Interfaces for VLSI Systems Using Tomlinson-Harashima Precoding

The data rate of interconnection has become an important factor in the achievement of high performance with very-large-scale integration (VLSI) systems. However, high-speed data transmission is difficult to achieve across interconnections such as microstrip lines and strip lines in VLSI systems. At high-speed data rates, interconnections behave as low-pass filters that cause intersymbol interference (ISI) and introduce bit errors at receivers. This paper proposes high-speed data transmission of 4-pulse amplitude modulation (PAM) (4-valued) signaling, using a Tomlinson-Harashima precoding (THP) technique. To realize the THP circuitry, digital multiplication and addition are required. To evaluate hardware costs, we investigate the required bit resolution for THP. Theoretical analysis and simulation results show that 6- to 8-bit digital resolution is necessary to remove a sufficient amount of ISI in 2-PAM (binary) at 3 Gbps over a microstrip line 2 [m].