Pre- and postsynthesis simulation mismatches

With the widespread adoption of top-down design methodologies using HDL and synthesis, RTL models have become the “golden” design database. However, ASIC and FPGA vendors still require a gate level netlist as the official sign-off design. Model ambiguities in RTL designs can cause differences between RTL and synthesized netlist designs. These differences in the best case cause simulation mismatches between RTL and gate designs. In the worst case, if not detected in simulation they can result in faulty hardware. This paper covers common sources of ambiguity in RTL models. Solutions are provided for avoiding these situations. Some basic simulation debug tips are provided to help identify these errors in simulation with both VHDL and Verilog. These examples are based on Synergy (Cadence´s synthesis tool) but also apply to synthesis in general