Title :
A 1.7mW 11b 250MS/s 2× interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS
Author :
Verbruggen, Bob ; Iriguchi, Masao ; Craninckx, Jan
Author_Institution :
imec, Leuven, Belgium
Abstract :
In recent years ADC research has resulted in impressive advances in power efficiency. SAR ADCs have reached energies per conversion step below 10fJ, but only at rather low sampling frequencies [1] or moderate resolution [2]. Wireless receivers for next-generation, higher-bandwidth standards such as LTE-advanced, however, will require much faster ADCs. We present a fully dynamic, two-times interleaved pipelined SAR ADC that achieves 10fJ/conversion-step with 9.5 ENOB at a sampling speed as high as 250MS/s.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; next generation networks; pipeline processing; power aware computing; radio receivers; digital CMOS; higher-bandwidth standards; interleaved fully dynamic pipelined SAR ADC; low sampling frequency; next generation wireless receiver; power 1.7 mW; power efficiency; size 40 nm; two-times interleaved pipelined SAR ADC; CMOS integrated circuits; Capacitance; Clocks; Frequency measurement; Noise; Transistors;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-0376-7
DOI :
10.1109/ISSCC.2012.6177093
