SiGe-On-Insulator (SGOI): substrate preparation and MOSFET fabrication for electron mobility evaluation

Author

Zhi-Yuan Cheng ; Currie, M.T. ; Leitz, C.W. ; Taraschi, G. ; Pitera, A. ; Lee, M.L. ; Langdo, T.A. ; Hoyt, J.L. ; Antoniadis, D.A. ; Fitzgerald, E.A.

Author_Institution

Microsystems Technol. Lab., MIT, Cambridge, MA, USA

fYear

2001

Firstpage

13

Lastpage

14

Abstract

Relaxed Si/sub 1-x/Ge/sub x/-on-insulator (SGOI) is a very promising technology, as it combines the benefits of two advanced technologies: the conventional SOI technology and the SiGe technology. SiGe-based devices have shown advantageous DC and RF performance using, the enhanced electronic properties associated with strain engineering and heterojunction energy barriers. SGOI is a versatile substrate that can be used to integrate various device structures, such as strained-Si and strained-SiGe FETs, and III-V optoelectronics. In this work, we have fabricated SGOI substrates via two different approaches. We also demonstrate strained-Si nMOSFET fabrication on SGOI and electron mobility enhancement is evaluated.

Keywords

Ge-Si alloys; MOSFET; annealing; buried layers; chemical mechanical polishing; electron mobility; etching; ion implantation; silicon-on-insulator; wafer bonding; CMP; MOSFET fabrication; SGOI technology; SiGe; SiGe-on-insulator; TEM; anneal; bond strength; dislocation density; electron mobility evaluation; etch pit density; etch-back approach; large-area ring structure; relaxed layer; smart-cut approach; strained-Si nMOSFET; substrate preparation; Capacitive sensors; Energy barrier; FETs; Germanium silicon alloys; Heterojunctions; III-V semiconductor materials; MOSFET circuits; Power engineering and energy; Radio frequency; Silicon germanium;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2001 IEEE International

Conference_Location

Durango, CO, USA

ISSN

1078-621X

Print_ISBN

0-7803-6739-1

Type

conf

DOI

10.1109/SOIC.2001.957961

Filename

957961