DocumentCode
1668294
Title
An 8 Gb multi-level NAND flash memory with 63 nm STI CMOS process technology
Author
Byeon, Dae-Seok ; Lee, Sung-Soo ; Lim, Young-Ho ; Park, Jin-Sung ; Han, Wook-Kee ; Kwak, Pan-Suk ; Kim, Dong-Hwan ; Chae, Dong-Hyuk ; Moon, Seung-Hyun ; Lee, Seung-Jae ; Hyun-Chul Cho ; Lee, Jung-Woo ; Moo-Sung Kim ; Yang, Joon-Sung ; Park, Young-Woo ; Ba
fYear
2005
Firstpage
46
Abstract
An 8 Gb multi-level NAND flash memory is fabricated in a 63 nm CMOS technology with shallow trench isolation. The cell and chip sizes are 0.02 /spl mu/m/sup 2/ and 133 mm/sup 2/, respectively. Performance improves to 4.4 MB/s by using the 2/spl times/ program mode and by decreasing the cycle time from 50 ns to 30 ns. This also improves the read throughput to 23 MB/s.
Keywords
CMOS memory circuits; flash memories; integrated circuit design; logic design; 23 MB/s; 30 ns; 4.4 MB/s; 50 ns; 63 nm; 8 Gbit; CMOS process technology; cell size; chip size; cycle time; multi-level NAND flash memory; program mode; read throughput; shallow trench isolation; CMOS process; CMOS technology; Circuit noise; Digital audio players; Digital cameras; Latches; Moon; Noise reduction; Threshold voltage; Universal Serial Bus;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
0-7803-8904-2
Type
conf
DOI
10.1109/ISSCC.2005.1493861
Filename
1493861
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