YAGLE, a second generation functional abstractor for CMOS VLSI circuits

Author

Lester, A. ; Bazargan-Sabet, P. ; Greiner, A.

Author_Institution

LIP6/ASIM Lab., Univ. Pierre et Marie Curie, Paris, France

fYear

1998

fDate

6/20/1905 12:00:00 AM

Firstpage

265

Lastpage

268

Abstract

This paper presents a new functional abstraction tool for CMOS VLSI. The tool uses a procedure called circuit disassembly in order to extract an oriented gate netlist from a transistor netlist. Logic equations are then generated for these extracted gates in order to produce a VHDL data-flow description for a circuit. This tool combines an advanced functional analysis technique with subgraph isomorphism algorithms in order to handle the widest possible number of circuit styles with a minimum of user intervention

Keywords

CMOS integrated circuits; VLSI; functional analysis; integrated circuit design; CMOS VLSI circuit; VHDL data flow model; YAGLE; circuit disassembly; design verification; functional analysis; logic equation; oriented gate netlist; second generation functional abstractor; subgraph isomorphism algorithm; transistor netlist; Assembly; CMOS logic circuits; Equations; Functional analysis; Laboratories; Logic circuits; Logic design; Process design; Transistors; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 1998. ICM '98. Proceedings of the Tenth International Conference on

Conference_Location

Monastir

Print_ISBN

0-7803-4969-5

Type

conf

DOI

10.1109/ICM.1998.825615

Filename

825615