DocumentCode :
1669075
Title :
A novel shallow trench isolation technology using LPCVD MTO/SiN liner in SOI wafer
Author :
Lee, Tien Jung ; Park, DaeLim ; Roh, Y.H. ; Kim, B.S. ; Ahn, D.H. ; Kim, E.H. ; Jeon, C.H. ; Kim, Y.W. ; Lee, S.C. ; Choi, C.S. ; Suh, K.P.
Author_Institution :
SOC Tech. Team, Samsung Electron. Co., Yongin, South Korea
fYear :
2001
Firstpage :
83
Lastpage :
84
Abstract :
A novel Shallow Trench Isolation (STI) technology has been proposed for the device fabrication using SOI wafers. The trench sidewall oxidation is replaced with MTO (Medium Temperature Oxide) and Silicon Nitride (SiN) to prevent the SOI bending problem. SiN Liner over MTO scheme showed the additional benefits such as reduced field oxide recess and improved gate oxide quality, Stress Induced Leakage Current (SILC) and Time Zero Dielectric Breakdown (TZDB). We also compared the bonded SOI and SIMOX wafers in terms of the gate oxide quality for the different STI liner schemes.
Keywords :
SIMOX; electric breakdown; elemental semiconductors; isolation technology; leakage currents; nitridation; oxidation; silicon; silicon compounds; silicon-on-insulator; LPCVD MTO/SiN liner; SIMOX wafers; SOI bending; SOI wafer; Si-Si/sub 3/N/sub 4/; Si-SiO/sub 2/; bonded SOI; device fabrication; gate oxide quality; medium temperature oxide; reduced field oxide recess; shallow trench isolation technology; silicon nitride; stress induced leakage current; time zero dielectric breakdown; trench sidewall oxidation; Degradation; Etching; Fabrication; Isolation technology; Leakage current; MOSFETs; Silicon compounds; Stress; Voltage; Wafer bonding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOI Conference, 2001 IEEE International
Conference_Location :
Durango, CO, USA
ISSN :
1078-621X
Print_ISBN :
0-7803-6739-1
Type :
conf
DOI :
10.1109/SOIC.2001.957996
Filename :
957996
Link To Document :
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