A comprehensive smart and stochastic methodology for optimum wire segmentation in nano scale FPGAs

The wire segmentation scheme, the ratio of each wire segment element, and the routing switch type, all as routing resources play an important role in the overall performance of FPGAs. This paper presents a smart comprehensive approach to achieve an efficient wire segmentation scheme, and a proper routing switch style for optimum performance of FPGAs in terms of output signal features such as delay, power, area, and routing channel width. In this work, 20 standard benchmark circuits have been used for the study, and extensive simulations have been performed to obtain a reliable segmentation model for the channel interconnects.