Evaluating manufacturability of radiation-hardened SOI substrates

Author

Alles, M. ; Dolan, B. ; Hughes, H. ; McMarr, P. ; Gouker, P. ; Liu, M.

Author_Institution

Ibis Technol. Corp., Danvers, MA, USA

fYear

2001

Firstpage

131

Lastpage

132

Abstract

The goal of this work was to transfer a radiation-hardening process to a commercial SOI wafer manufacturer, optimize the process for manufacturing and wafer quality, and demonstrate that the process is compatible with commercial SOI wafers. Over the period of the project three types of SOI substrates were examined having BOX thicknesses between 100 and 200 nm, consistent with the state-of-the-art substrates in use by radiation-hardened SOI and commercial SOI substrate users. Two different regimes for silicon thickness were examined, one for partially depleted and one for fully depleted target applications.

Keywords

CMOS integrated circuits; integrated circuit manufacture; radiation hardening (electronics); silicon-on-insulator; substrates; 100 to 200 nm; BOX thicknesses; SOI wafer manufacturer; Si; evaluating manufacturability; fully depleted target applications; partially depleted target applications; radiation-hardened SOI substrates; silicon thickness; wafer quality; CMOS technology; Circuits; Laboratories; Manufacturing; Materials testing; Radiation effects; Radiation hardening; Silicon; Space technology; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2001 IEEE International

Conference_Location

Durango, CO, USA

ISSN

1078-621X

Print_ISBN

0-7803-6739-1

Type

conf

DOI

10.1109/SOIC.2001.958021

Filename

958021