Congestion driven placement for Mesh-based FPGA architecture with local interconnect

In this paper we present an adaptation of a congestion driven placement technique to a Mesh based FPGA architecture containing a local interconnect connections. This techniques aims at spreading out congestion by considering white spaces and avoiding signals bounding boxes overlap. As shown in the experimentation section this technique reduces required routing channel width efficiently and consequently the device total area by 10% in average. In terms of circuit performance, we notice that congestion alleviation allows timing-driven router to reduce critical path delays despite wirelength increasing. This is due essentially to timing closure improvement.