A multistep extrapolated S-parameter model for arbitrary on-chip interconnect structures

Accurate high-frequency interconnect models are needed for the precise estimation of signal delays, crosstalk, and energy losses in complex on-chip communication structures, such as hierarchical bus architectures and networks-on-chip. In this paper we introduce a computationally-efficient wide-bandwidth characterization method based on an incremental extrapolation of S-parameters for arbitrary interconnect structures. Our method defines a systematic set of a priori parameter extractions and performs on-demand multistep extrapolations for interconnect segments with specified wire length, widths, spacings, metal layer, and neighboring routing information. Experimental evaluations show a maximum absolute error of less than 2·10^-2 (magnitude) and 7 degrees (angle) between our model and an industry-standard full-wave field simulator for a 90-nm CMOS process. We consistently enforce the passivity of the admittance matrices for each set of measured or generated parameters to eliminate the possible errors introduced during parameter measurements and extrapolation. Circuit-level simulations with the extrapolated model show a maximum signal delay error of less than 12.5% across multiple metal layers and wire configurations.