Efficient hardware design for the upsampling in the H.264/SVC scalable video coding extension

This paper presents the design of an efficient architecture for the upsampling method of the scalable extension of the H.264 video coding standard, also called H.264/SVC. This is the first hardware design reportted in the literature for the upsampling filter of the H.264/SVC standard. This hardware module is used between spatial layers in the scalability process. The upsampling architecture was designed to work in the context of an encoder or decoder with two dyadic spatial layers, with the QVGA resolution (320×240 pixels) for the base layer, and VGA resolution (640×480 pixels) for the enhancement layer. The architecture was described in VHDL and synthesized targeting Stratix II and Stratix IV Altera FPGAs and it was validated using the ModelSim simulation tool. The results obtained through the synthesis of the complete upsampling architecture shows that this architecture achieves processing rates between 384 and 409 frames per second when the synthesis is targeted to Stratix IV. The estimate for higher resolutions videos indicates processing rates between 96 and 103 frames per second for 4VGA resolution (1280×960 pixels). Considering the 16VGA resolution (2560×1920 pixels), the processing rate was estimated between 24 and 25 frames per second. With these results, The designed architecture reached processing rates sufficient to process input videos in real time.