DocumentCode :
1671395
Title :
High-tension power delivery: operating 0.18 μm CMOS digital logic at 5.4V
Author :
Rajapandian, Saravanan ; Shepard, Kenneth ; Hazucha, Peter ; Karnik, Tanay
Author_Institution :
Columbia Univ., New York, NY, USA
fYear :
2005
Firstpage :
298
Abstract :
A "high-tension" power-delivery system stacks CMOS logic domains to operate at multiples of the supply voltage without explicit downconverters. Experimental results are presented for a prototype system in a 0.18 μm technology operating at 3.6 V and 5.4 V. Peak energy efficiencies as high as 93% are demonstrated at 3.6 V.
Keywords :
CMOS logic circuits; voltage regulators; 0.18 micron; 3.6 V; 5.4 V; 93 percent; CMOS digital logic; energy efficiency; high-tension power delivery; level-shifting circuits; push-pull linear regulators; stacked logic domains; CMOS logic circuits; Capacitors; Delay; Driver circuits; Energy efficiency; Impedance; Inverters; Logic devices; Regulators; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0193-6530
Print_ISBN :
0-7803-8904-2
Type :
conf
DOI :
10.1109/ISSCC.2005.1493987
Filename :
1493987
Link To Document :
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